1. Field of the Invention
The present invention generally relates to a static random access memory (SRAM) having a thin film transistor load and, more particularly, to a static random access memory cell structure having a thin film transistor load in which a data hold capability can be enhanced and an immunity for soft error caused by .alpha.-particle or the like can be improved.
2. Description of the Prior Art
Recently, a CMOS (complementary metal oxide semiconductor) type SRAM (static random access memory) that utilizes a CMOS inverter receives a remarkable attention as a SRAM capable of reducing its electric power consumption. The CMOS circuit, however, needs a region in which an N-MOS transistor and a P-MOS transistor are separated. There is then the problem that the CMOS circuit is disadvantageous when an integration level is increased.
It has been proposed so far to increase an integration level by forming a load P-MOS transistor of a reverse-stagger type TFT (thin film transistor). That is, by laminating a P-channel TFT (hereinafter simply referred to as a P-TFT) on the N-MOS transistor, an occupied area of the C-MOS circuit can be reduced considerably, which can realize the highly-integrated CMOS type SRAM with ease.
A structure of a conventional CMOS-type SRAM will be described with reference to FIG. 1 forming an equivalent circuit diagram and FIG. 2 forming a cross-sectional view thereof.
As shown in FIG. 1, the conventional SRAM includes a memory cell which comprises a flip-flop circuit FF formed of loads of a pair of driver transistors (N-MOS transistors) Tr.sub.1, Tr.sub.2 and a pair of P-channel thin film transistors (hereinafter simply referred to as P-TFTs) T.sub.1, T.sub.2 coupled to memory nodes N.sub.1, N.sub.2 of the driver transistors Tr.sub.1, Tr.sub.2 and a pair of access transistors (N-MOS transistors ) Q.sub.1, Q.sub.2. In FIG. 1, reference symbol WL denotes a word line and reference symbols BL and (invertled BL) denote, bit lines.
A structure of SRAM will be described with reference to FIG. 2. As shown in FIG. 2, a gate electrode GD.sub.1 of the driver transistor Tr.sub.1 and a gate electrode (word line) of the access transistor Q.sub.2 are formed on a P-type well region 31 over a gate insulating film 32 made of SiO.sub.2 or the like by a first semiconductor layer, for example, a polycide layer. Gate electrodes GT.sub.1, GT.sub.2 of P-TFT (T.sub.1 and T.sub.2) are formed on the gate electrode GD.sub.1 with an interlevel insulator 33 made of SiO.sub.2 by a second semiconductor layer, for example, a polycrystalline silicon layer. An active layer Ac.sub.1 of P-TFT (T.sub.1) and a Vcc line 35 are formed on the gate electrodes GT.sub.1 and GT.sub.2 with an interlevel insulator 34 made of SiO.sub.2.
The memory node N.sub.1 is formed at the connected portion of the gate electrode GD.sub.1 of the driver transistor Tr.sub.1 and one source-drain region SD of the access transistor Q.sub.2. In FIG. 2, reference numerals 36, 37 designate interlevel insulators made of SiO.sub.2, reference numeral 38 designates a bit line deriving wiring made of a metal film (e.g., Al film). Reference numeral 39 designates a P-type silicon substrate and 40 an N-type well region.
According to the prior art, in order to prevent soft error from being caused by .alpha.-particle or the like, the gate electrode GT.sub.1 of the P-TFT (T.sub.1) is extended up to the lower portion of a drain region 41D that is connected to the memory node N.sub.1 of the active layer Ac.sub.1, thereby forming a coupling capacitance between the gate electrode GT.sub.1 and the drain region 41D. A coupling capacitance is formed also between the gate electrode GT.sub.1 of the P-TFT (T.sub.1) and the gate electrode GD.sub.1 of the driver transistor Tr.sub.1.
An equivalent circuit of the above-mentioned structure shown in FIG. 2 is represented in FIG. 1, wherein the memory nodes N.sub.1 and N.sub.2 are coupled by a coupling capacitance C. The aforesaid soft error can be suppressed by the coupling capacitance C (see IEDM 88, pp. 48 to 51 "A 25 .mu.m.sup.2, New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity").
As is clear from FIG. 2, the coupling capacitance C in the SRAM is formed on the upper portion of the driver transistor Tr.sub.1 and a capacitance value thereof is determined by an area that is substantially determined by the layout of the SRAM.
If a soft error immunity is improved by increasing the capacitance value, then a memory cell size of the SRAM must be increased or the insulating film 34 serving as a dielectric film of the coupling capacitance formed between the gate electrode GT.sub.1 and the drain region 41D must be reduced in thickness.
The increase of memory cell size contradicts the increase of capacitance. Also, if the insulating film 34 serving as the dielectric film of the coupling capacitance C is reduced in thickness, then a withstand voltage, yield, TDDB life or the like will be degraded. Therefore, the increase of capacitance value cannot be realized with ease.
Furthermore, in the SRAM, the source region 41S of the P-TFT (T.sub.1, T.sub.2) becomes a Vcc power supply line directly. Consequently, in order to lower its wiring resistance, the source region 41S and the drain region 41D of the P-TFT (T.sub.1, T.sub.2) are formed with high impurity concentration higher than 10.sup.19 cm.sup.-3 at the same time.
When the coupling capacitance is formed at the overlapping portion of the drain region 41D having high impurity concentration and the gate electrodes GT.sub.1, GT.sub.2, if a gate electric field is applied to the drain region 41D, then a drain leakage current due to a tunneling current in energy band occurs at the drain region end adjoining to the channel region 41C. Consequently, an off-state current of the P-TFT (T.sub.1, T.sub.2) is raised.